This e-book contains United States Patent Statute (United States Code, Title 35) – 2013 Edition, including the September 16, 2011 Amendments of the Leahy-Smith America Invents Act (AIA), the January 14, 2013 Technical Amendments to the AIA, and the December 18, 2012 Hague Agreement additions. The e-book is prepared with a convenient table of contents for easy navigation of the various statutes.

The text contains the verbatim text of the 35 U.S.C. §§ 1-390, including the statutory text, historical and revision notes, and amendments. Source: public domain materials that may be found at http://uscode.house.gov, dated August 14, 2013.

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With U.S. patent law taking on an ever more international perspective, and with the difficulties faced by businesses that would like to seek protection of their intellectual property internationally, it is increasingly important that the proper territorial scope and reach of patent law is well defined. The question of the exact territorial reach of U.S. patent law is particularly pertinent to transnational “offer to sell” infringement liability—liability for patent infringement based only on an offer to sell a U.S.-patented product. The Federal Circuit has only very recently directly addressed this issue. This court has acknowledged that when two U.S. companies make an offer to sell in a foreign country, contemplating a sale in the United States, there is potential liability for infringement under U.S. patent laws. The court did not directly address, however, other potential scenarios, such as when two companies make an offer in the United States which contemplates a sale in a foreign country. Thus, although the territorial scope of “offer to sell” infringement is clearer now than it has been in the past, questions still remain.

In an effort to provide some clarity to the scope of “offer to sell” infringement, this Note proposes the adoption and application of a clear rule to all “offer to sell” transnational patent infringement cases. This rule, the “Location of the Contemplated Sale” rule, clearly defines the bounds of “offer to sell” infringement under U.S. patent law and specifies that the location of the contemplated sale should control when deciding whether there is “offer to sell” infringement. This rule extends the Federal Circuit’s reasoning, providing a clear guide for all potential situations while also respecting the policies underlying “offer to sell” infringement.

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The paper attempts to briefly outline some of the differences between French and American copyright law. The differences between the two copyright systems are partly a result of the differing philosophical underpinnings of the two systems. The natural law underpinnings of the French copyright system, for example, are manifest in the moral rights granted to authors. The American system is founded primarily on an economic philosophy, and accordingly does not include the granting of moral rights to authors. These different philosophies result in potentially significant differences in the ability of authors to license or assign their works to others. This paper will briefly discuss these and other issues, while comparing French and American copyright laws.

A. Market Definition

The U.S. smartphone market consists of all firms throughout the world that manufacture and sell smartphones to U.S. consumers. A smartphone is a mobile electronic device which runs an advanced operating system that is open to installing new applications, is always connected to the internet, and which provides very diverse functionality to the consumer.

The major participants in the U.S. smartphone market include Apple Inc. (a U.S. corporation), Research in Motion Limited (or RIM, a Canadian corporation), HTC Corporation (a Taiwanese corporation), Motorola, Inc. (a U.S. corporation), and Samsung Electronics Co. Ltd. (a subsidiary of the Korean corporation Samsung Group). Smaller participants include HP/Palm, Inc. (a subsidiary of HP, a U.S. corporation), LG Corp. (a Korean corporation), and Nokia Corporation (a Finnish corporation).

B. Threat Analysis

In general the smartphone market is rapidly changing, with constant product introductions. It is characterized by quickly evolving technology and designs, short product life cycles, aggressive pricing, rapid imitation of product and technological advancements, and highly price sensitive consumers. Self-elasticity and cross-elasticity are high. No one firm in the market has sufficient market share to control prices, resulting is strong rivalry and competitive pricing. The barriers to entry are high due to the existence of patents, high fixed costs and economies of scale, regulation, and brand loyalty.

The individual market participants engage in attempts at product differentiation, some being more successful than others. The standout is Apple, which has successfully differentiated its iPhone, and stands a good chance of maintaining that differentiation due to its closed and all-inclusive model or development and use.

C. Intermarket Effects

Intermarket effects are significant in the U.S. smartphone market. Multiple other markets have an effect on the U.S. smartphone market: from the suppliers, to the industrial designers, to the distributors, to the retailers, to the network service providers. Smartphone manufacturers make contracts with the network service providers for exclusivity of certain phones, and the providers in turn subsidize the cost of the smartphone for the consumer. Every smartphone user must purchase service with their smartphone, or the value of the smartphone is significantly diminished.

While technology scaling has presented many new and exciting opportunities, new design challenges have arisen. Smaller feature sizes have led to increased density and large variations in the delay and power characteristics of on-chip devices. Additionally, with the increasing desirability of low-power chips, decreasing power consumption has become a significant priority. Major sources of dynamic power consumption in modern chips include glitches (i.e., spurious signal transitions), the reduction of which are challenges to circuit designers. High-level synthesis has been touted as a solution to these problems, as it can both significantly reduce the number of man hours required for a circuit design, and offer greater opportunities for optimization of design goals, by raising the level of abstraction. In this thesis, we present two resource binding and allocation algorithms that take advantage of the optimization opportunities available at the higher level of abstraction.

The first is a new variation-aware high-level synthesis binding and module selection algorithm, named FastYield, which takes into consideration multiplexers, functional units, registers, and interconnects. FastYield connects with the lower levels of the design hierarchy through its inclusion of a timing-driven floorplanner guided by a statistical static timing analysis engine which is used to modify and enhance the synthesis solution. FastYield is able to incorporate spatial correlations of process variations in its optimization, which are shown to affect performance yield. FastYield is shown to achieve a significant reduction in clock period, and significant gain in performance yield, when compared to a variation-unaware and layout-unaware algorithm.

The second is a glitch-aware, high-level binding algorithm for power, area, and multiplexer reduction targeting field programmable gate arrays (FPGAs), called HLPower. HLPower employs a glitch-aware dynamic power estimation technique derived from an FPGA technology mapper. High-level binding results are converted to VHSIC hardware description language (VHDL), and synthesized with Altera’s Quartus II software, targeting the Cyclone II FPGA architecture. Power characteristics are evaluated with the Altera PowerPlay Power Analyzer. The binding results of HLPower are compared to LOPASS, a state-of-the-art low-power high-level synthesis algorithm for FPGAs. Experimental results show that HLPower significantly reduces toggle rate and area, resulting in a large decrease in dynamic power consumption.

Resource binding, a key step encountered in behavioral synthesis, has been studied intensively in the past. Among the published results, resource binding to reduce switching activity (SA) of the design for minimizing dynamic power has been one of the actively-pursued topics. Two types of SAs can be minimized: the intra−transition SA and the inter−transition SA. Previous work either ignored the inter-transition SA or provided heuristic to deal with it. When the inter-transition SA was considered, it was not clear previously whether the problem could still be solved optimally. In this paper, for the first time, we demonstrate that resource binding considering inter-transition SAs can be solved in polynomial time for designs that can be represented by data-flow graphs (DFG). This is realized by transforming the problem into finding the shortest path problem in a k-dimensional graph. We also propose an efficient heuristic that uses a network-flow algorithm followed by a legalization step using a bipartite matching algorithm. Experimental results show that a considerable amount of SA reduction can be obtained compared to the previous state-of-the-art results.

Glitches (i.e. spurious signal transitions) are major sources of dynamic power consumption in modern FPGAs. In this paper, we present an FPGA-targeted, glitch-aware, high-level binding algorithm for power and area reduction, accomplished via dynamic power estimation and multiplexer balancing. Our binding algorithm employs a glitch-aware dynamic power estimation technique derived from the FPGA technology mapper in Cheng2007. High-level binding results are converted to VHDL, and synthesized with Altera’s Quartus II software, targeting the Cyclone II FPGA architecture. Power characteristics are evaluated with the Altera PowerPlay Power Analyzer. The binding results of our algorithm are compared to LOPASS, a state-of-the-art low-power high-level synthesis algorithm for FPGAs. Experimental results show that our algorithm, on average, reduces toggle rate by 22% and area by 9%, resulting in a decrease in dynamic power consumption of 19%. To the best of our knowledge this is the first high-level binding algorithm targeting FPGAs that considers glitch power.

While technology scaling has presented many new and exciting opportunities, new design challenges have arisen due to increased density, and delay and power variations. High-level synthesis has been touted as a solution to these problems, as it can significantly reduce the number of man hours required for a design by raising the level of abstraction. In this paper, we propose a new variation-aware high-level synthesis bind-ing/module selection algorithm, named FastYield, which takes into consideration multiplexers, functional units, registers, and interconnects. Additionally, FastYield connects with the lower levels of the design hierarchy through its inclusion of a timing driven floorplanner guided by a statistical static timing analysis (SSTA) engine which is used to modify/enhance the synthesis solution. FastYield is able to incorporate spatial correlations of process variations in its optimization, which are shown to affect performance yield. On average, FastYield achieves a clock peri-od that is 14.5% smaller, and a performance yield gain of 78.9%, when compared to a variation-unaware algorithm. By making use of accurate timing information, FastYield’s rebinding improves performance yield by an average of 9.8% over the initial binding, for the same clock period. To the best of our knowledge, this is the first high-level synthesis binding/module selection algorithm that is layout-driven and variation aware.

Billions of devices on a chip is around the corner and the trend of deep submicron (DSM) technology scaling will continue for at least another decade. Meanwhile, designers also face severe on-chip parameter variations, soft/hard errors, and high leakage power. How to use these billions of devices to deliver power-efficient, high-performance, and yet error-resilient computation is a challenging task. In this paper, we attempt to demonstrate some of our perspectives to address these critical issues. We elaborate on variation-aware synthesis, holistic error modeling, reliable multicore, and synthesis for application-specific multicore. We also present some of our insights for future reliable computing.

Microfluidics and “lab-on-chips” are currently major areas of research. Integrated chips provide many advantages over the current macroscopic methods in biological applications such as increased throughput, better automation, reduced reagent consumption, increased surface/volume ratios and stable laminar flows. Unfortunately, the control of flows in microchannels has special challenges, and conventional flow control tools such as syringes or peristaltic pumps are generally poorly adapted. In order to facilitate the further development of a lab-on-chip system for single cell analysis, a special control system based on hydrostatic pressure is used. The system is compact, portable, inexpensive, and computer-interfaced for precise control and ease of use. The level of fluid in various reservoirs is changed by a computer-controlled servo to create pressure differences. The change in fluid level causes flow through the channels in the chip. A detailed description of the system is presented. Further development of the system is possible and could lead to many improvements and adaptations for specific applications.

As a II-VI compound semiconductor with a wide and direct band gap of 3.37 eV, ZnO nanowires have attracted intensive research effort due to their unique properties and potential application as transistors, light-emitting diodes, photodetectors, and chemical sensors. Studies of the electrical transport characteristics, as well as the optical properties and mechanical properties of individual ZnO nanowires have been reported recently. In this report, the characteristics of suspended nanowires are presented. Single-crystalline ZnO nanowires are synthesized by a vapor trapping chemical vapor deposition method. They are configured as field-effect transistors (FET) with a suspended ZnO nanowire channel. Contacts between the ZnO nanowire and metal electrodes are improved through annealing and metal deposition using a focused ion beam. The gas sensing characteristics are studied and compared to those of the nonsuspended structure. In addition, the surface potential distribution of the suspended nanowire is investigated using scanning probe microscopy to characterize the uniformity of the nanowire. Continued work is underway to reveal the intrinsic properties of suspended ZnO nanowires and to explore their device applications.