I and my colleagues, Greg Lucas and Deming Chen, were given a best paper award for our submission to one of the premier, peer-reviewed, international conferences on electronic design automation, the Asia South Pacific Design Automation Conference (ASP-DAC), held in Yokohama, Japan in January 2009. This year ASP-DAC had an acceptance rate of 31%, with the number of submissions totaling more than 350, and Best Paper Awards going to 2 papers, making receiving such an award quite an honor.
A picture of the event, which I was unable to attend, can be seen here.
ECE Illinois news article on the award can be found here, and is reprinted below.
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ECE Headline News
Graduate students and professor team up to win “Best Paper” award
Charlie Johnson, ECE ILLINOIS
March 11, 2009
Dr. Kazutoshi Wakabayashi (right), the general chair of the IEEE/ACM Asia and South Pacific Design Automation Conference, presents the Best Paper Award to ECE Assistant Professor Deming Chen (left) and graduate student Greg Lucas. ECE graduate student Scott Cromar, who also co-authored the paper, was unable to attend the conference.
Designing better, faster computer chips and winning awards at the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)–Greg Lucas can do that. Eating with chopsticks–that’s a challenge. Lucas, a PhD candidate in ECE is part of the trio that also included fellow ECE graduate student Scott Cromar and ECE Assistant Professor Deming Chen who were recently awarded the ASP-DAC’s Best Paper Award for their paper “FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization.”
The paper was one of two to win “Best Paper” out of more than 350 submitted to the conference from around the world. The award was presented in late January at the ASP-DAC’s 14th annual meeting at the Pacifico Yokohama in Yokohama, Japan.
“It was pretty surprising at first. I don’t think we were really expecting it. We were just hoping to get accepted,” said Lucas.
“It’s cool to win, especially because it’s the first paper that we produced as graduate students,” said Cromar.
The goal of the team was to develop software tools to boost performance yield and help engineers design circuits more quickly and at higher quality. The team focused on high-level synthesis that could automatically convert design specifications from a higher-level specification, such as C or C++, to a lower-level description in the VHDL computer language. This process would dramatically improve design productivity and design quality.
But, in order to achieve their goal, the team had to overcome several roadblocks. The high level of abstraction makes optimizing circuit performance difficult, and a gap can frequently exist between performing at a higher level and transcribing that performance to a lower level. The team’s layout-driven high level synthesis is a viable way to bridge such a gap.
The team’s solution was to create a “floor plan” for the design to estimate the propagation delays of the critical signals that were back-annotated to high-level synthesis in order to introduce useful transformations. Another challenge arose from process variation, which is the industry’s inability to precisely control the circuit fabrication process of nanometer-scale technologies. Process variation can significantly reduce performance if not handled properly.
To combat the effects of process variation, a statistical design methodology based on accurate systematic and random variation models was developed by the team. Although other researchers have attempted solutions in the past to deal with layout and variation separately, this team stood out for their method of combining both layout and variation modeling together.
“You need a layout to be the basis for accurate variation modeling,” said Chen. “Without a layout, the variation models don’t really have a solid foundation no matter how fancy they look. On the other hand, when you have accurate variation models, you can use them to generate a better layout. These two factors actually work together.”
Compared to other algorithms that do not consider layout and variation together, the team’s “FastYield” method increased performance yield by 79%. Circuits with a higher performance yield have a better chance of meeting high performance targets. “It basically means that when we go to manufacture, we’re getting more for our money,” said Lucas.
Chen, Cromar, and Lucas received word that they had won the Best Paper award only a week before the conference was scheduled to take place. The team quickly made arrangements to fly to Japan to receive the award at the ASP-DAC, though Cromar stayed behind to care for his wife Catherine who was pregnant with twins. While the high-level research required to author such a high-quality paper was surely challenging, using chopsticks proved equally difficult for Lucas. “I ate lunch with people from three different countries, and I was the only one who couldn’t use chopsticks,” he said. “But, I figured it out because I thought they were going to make fun of me.”
Though Cromar is planning to graduate with his MSEE in the spring, Lucas and Chen hope to continue working on optimizing circuit performance exploring high-level design space. “Once you have this framework ready, we feel we have really opened up some windows,” said Chen. “Hopefully we can grow one or two PhD’s out of this.” Now that they both have chopsticks down, accepting future awards should prove much easier.
This project was sponsored by the National Science Foundation.