Graduate Thesis
S. Cromar, “High-Level Resource Binding and Allocation for Power and Performance Optimization,” Master’s Thesis, May 2009.
Graduate Research (U of I)
D. Chen and S. Cromar, “An Optimal Resource Binding Algorithm with Inter-Transition Switching Activities for Low Power,” Journal of Low Power Electronics, Volume 5, Number 4, December 2009. (No free version available.)
S. Cromar, J. Lee, and D. Chen, “FPGA-Targeted High-Level Binding Algorithm for Power and Area Reduction with Glitch-Estimation,” IEEE/ACM Design Automation Conference, July 2009.
G. Lucas, S. Cromar, and D. Chen, “FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization,” IEEE/ACM Asia and South Pacific Design Automation Conference, January 2009. (Best Paper Award)
S. Akram, S. Cromar, G. Lucas, A. Papakonstantinou, and D. Chen, “VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip,” IEEE/ACM Asia and South Pacific Design Automation Conference, January 2008. (Invited)
Undergraduate Research (UCI)
S. Cromar, “Computer-interfaced, Servo-actuated Microfluidic Control System for Single Cell Analysis,” 2006.
S. Cromar, “Properties of Suspended ZnO Nanowire Field-Effect Transistor,” 2006. Presented at the 2006 University of California, Irvine, Integrated Micro/Nano Summer Undergraduate Research Experience Symposium.
